In the semiconductor fabrication industry, during formation of local interconnect lines (LILs) to e.g. active and passive devices of metal-oxide semiconductor (CMOS) structures, inter-layer dielectric (ILD) materials such as oxides and etch-stop materials such as nitrides of the CMOS structures are typically etched and then filled with e.g. W.
The LILs are typically made up of structures referred to as holes and slits. During simultaneous etching of the holes and slits during fabrication of the LILs, a number of problems may occur, such as under-etching of holes. Under-etching of holes causes failure to make electrical contact to the active regions of the CMOS structures. Holes may be under-etched when etched simultaneously with slits, due to a faster etching rate of slits as the latter typically possess larger exposed areas than holes.
In order to address this problem, the etching time is typically increased. However, when etching holes and slits simultaneously, due to the faster etching rate of slits, increasing etching time may typically cause over-etching of the slits. It is therefore desirable to improve the selectivity during the etching of the holes and slits to avoid or reduce unwanted etching of in particular the shallow trench isolation (STI) oxide underneath the etch-stop material. Over-etching into the STI may give rise to junction leakages and thus yield losses during fabrication of CMOS structures.
The above mentioned problem in avoiding over-etching of slits is particularly significant where different types of CMOS structures are fabricated on a single wafer, which is often the case. For example, different CMOS structures fabricated on a wafer may include flash memory modules, static random access memory (SRAM), Logic modules, and control modules (PCM). Table 1 lists typical thicknesses of the ILD material and the etch-stop material in different CMOS structures. As would be appreciated by a person skilled in the art, the variations in thicknesses of the ILD material and the etch-stop material significantly increase the difficulty of choosing a suitable etching time in the processing of such wafers such that yield losses may be reduced. Different ILD and etch-stop material thicknesses within a wafer may be inherent to the typography and pattern density, in particular for poly lines, in the relevant regions.
TABLE 1ThicknessPCMSRAM/LogicFlashILD material (Angstroms)9000900011000Etch-stop material (Angstroms)950900500